Silicon Wafers & Substrates

Product Structures

Product Type	Main Characteristics	Typical Selection Direction
Monocrystalline silicon wafers	Uniform crystal structure and a stable, flat surface.	Device research, MEMS, sensors, thin-film deposition, and process development.
Single-side polished wafers (SSP)	One polished process surface, with a backside that may be etched or non-polished.	Front-side coating, lithography, processing, and surface characterization.
Double-side polished wafers (DSP)	Low-roughness polished surfaces on both sides.	Backside alignment, double-side lithography, optical inspection, bonding, and precision processing.
Thermally oxidized silicon wafers	A controlled silicon dioxide layer formed on the silicon surface.	Insulation, dielectric layers, masking, passivation, and surface studies.
SOI wafers	Device layer, buried insulating layer, and supporting silicon layer.	MEMS, microsensors, isolation structures, and advanced device research.
High-resistivity silicon wafers	Higher electrical resistivity to reduce substrate conduction.	RF, microwave, power devices, sensors, and electrical measurements.

Conductivity Type and Resistivity

Selection Factor	Common Options	Selection Considerations
N-Type silicon	Donor-doped silicon	Use when an N-type substrate or defined carrier behavior is required.
P-Type silicon	Acceptor-doped silicon	Use when a P-type substrate is required for device fabrication or comparison studies.
Low-resistivity silicon	Low-resistivity or heavily doped configurations	Useful when electrical conduction, backside contact, or current transport is important.
Medium-resistivity silicon	General-purpose resistivity ranges	Suitable for general device development, process validation, and material research.
High-resistivity silicon	High-resistivity, ultra-high-resistivity, or undoped configurations	Suitable for reducing parasitic conduction, RF loss, and electrical background effects.

Resistivity should be selected together with the device structure, test frequency, contact design, doping requirements, and downstream process. For electrically sensitive applications, specifying only N-Type or P-Type may not be sufficient; the target resistivity range should also be defined.

Wafer Diameter

Wafer Size	Typical Use Direction
2 inch	Small-scale experiments, material screening, early process validation, and sample-level research.
3 inch	Small-batch process development, MEMS, and sensor research.
4 inch	Common laboratory lithography, deposition, etching, and device-development processes.
6 inch	Larger-area process validation, process transfer, and multiple-device layouts.
8 inch	Large-area process development, equipment compatibility studies, and improved usable area.

Choose the diameter according to the available chuck, chamber, wafer carrier, mask, alignment system, and inspection equipment. A larger wafer is not automatically the better choice; equipment compatibility and usable process area are more important.

Surface Finish and Geometry

Important wafer specifications may include:

• Single-side or double-side polishing
• Surface roughness
• Nominal thickness and thickness tolerance
• Total thickness variation (TTV)
• Bow and warp
• Backside condition
• Edge profile and orientation notch

For general material research, diameter, thickness, and polishing are usually the first specifications to confirm. For lithography, bonding, deposition, and double-side processing, TTV, bow, warp, and backside roughness may also be critical.

Crystal Orientation

Orientation	Selection Direction
<100>	Widely used for semiconductor processing, MEMS, lithography, and surface fabrication.
<111>	Used for specific etching behavior, surface structures, and crystallographic studies.
Custom orientation	Suitable when crystal-plane direction or etching behavior is process-specific.

Crystal orientation can affect wet etching, surface atomic arrangement, thin-film growth, and device direction. If the process depends on a particular crystal plane, confirm the orientation and allowable deviation before ordering.

Thermal Oxide Silicon Wafers

Thermally oxidized silicon wafers combine a silicon substrate with a defined silicon dioxide layer. They can be selected according to oxide thickness, oxidation side, base wafer diameter, conductivity type, thickness, and surface finish.

Parameter	Selection Direction
Oxidation side	Single-side or double-side oxidation.
Oxide thickness	Thin, medium, or application-specific customized thickness.
Base polish	SSP or DSP silicon substrate.
Base conductivity	N-Type, P-Type, high-resistivity, or another specified silicon base.
Functional use	Insulation, dielectric layers, masking, passivation, surface protection, or process comparison.

How to Select a Silicon Wafer

1. Confirm the wafer diameter supported by your equipment.
2. Select N-Type, P-Type, high-resistivity, or undoped silicon according to the device and test requirements.
3. Define the target resistivity range.
4. Choose SSP or DSP according to the processing surfaces required.
5. Select thickness based on equipment clamping, process depth, and mechanical strength.
6. Confirm TTV, bow, and warp requirements for lithography, bonding, deposition, or double-side processing.
7. Select a thermal oxide or SOI structure when insulation or an integrated dielectric layer is required.
8. Confirm crystal orientation, edge profile, notch, cleanliness, and packaging requirements.

Typical Applications

• Semiconductor device research and process validation
• MEMS and microsensor fabrication
• Lithography, etching, deposition, and surface-treatment studies
• Thin-film growth and interface research
• RF, microwave, and electrical testing
• Power-device and isolation-structure research
• Thermal oxidation, dielectric-layer, and passivation experiments
• Optical, materials, and nanofabrication research
• Process development in university, institutional, and industrial laboratories

Frequently Asked Questions