Atomic Precision at the 2nm Node
As semiconductor manufacturing advances toward 2nm nodes, atomic layer etching (ALE) has become essential for achieving sub-3nm feature dimensions. Unlike conventional reactive ion etching, ALE operates through self-limiting surface reactions that remove exactly one atomic layer per cycle. This process enables uniform etching across complex geometries, addressing critical challenges in line edge roughness and material selectivity.
Fundamental ALE Process Cycle
- Surface activation: Chemisorption of reactive species such as chlorine radicals on silicon surfaces
- Purge: Removal of excess reactants from the chamber
- Removal: Energetic ions or photons induce desorption of the modified atomic layer
- Purge: Evacuation of volatile byproducts before the next cycle
Key Performance Requirements for 2nm Nodes
| Parameter | Requirement at 2nm Node |
|---|---|
| Line edge roughness (RMS) | Below 0.5 nm |
| Si/SiO₂ selectivity | Greater than 200:1 |
| Si/SiN selectivity | Greater than 150:1 |
| Metal/dielectric selectivity | Greater than 100:1 |
Advanced ALE Techniques for Sub-3nm Fabrication
Plasma-Enhanced ALE (PE-ALE)
PE-ALE combines the atomic precision of thermal ALE with plasma activation to achieve higher throughput and better anisotropy control. This technique operates at lower process temperatures, reducing thermal stress on sensitive device structures. Ion energies are maintained between 5 eV and 20 eV to avoid substrate damage while ensuring complete removal of the modified layer.
Area-Selective Etching and Deposition
Integrating ALE with atomic layer deposition (ALD) enables self-aligned processes that rely on chemical selectivity rather than lithographic masks. This approach reduces edge placement errors and eliminates multiple lithography steps, which is critical for achieving the tight pitch requirements at 2nm nodes.
Process Optimization and Control
Surface Chemistry Engineering
- Metalorganic precursors for high-k dielectric materials
- Low-temperature reactive species for sensitive transistor structures
- Self-assembled monolayers serving as nanoscale etch masks
In-Situ Metrology for Atomic-Scale Monitoring
- Optical emission spectroscopy with sub-monolayer sensitivity
- Mass spectrometry for detecting single-cycle byproducts
- X-ray photoelectron spectroscopy for surface composition analysis
Integration Challenges and Solutions
Material Selectivity at Critical Interfaces
The shrinking gap between high-k dielectrics and metal gates demands selectivities exceeding 100:1. ALE achieves this through careful tuning of precursor chemistry and ion energy, ensuring that only the target material is removed without damaging adjacent layers.
Quantum Confinement Effects at 2nm Dimensions
At feature sizes below 3 nm, quantum effects begin to dominate material behavior. Electron transport during etching must be modeled with quantum mechanical considerations, and process parameters must be adapted to altered material properties at atomic scales.
Economic Considerations for Volume Manufacturing
| Factor | Impact on Manufacturing Cost |
|---|---|
| Slower etch rate vs. RIE | Higher per-wafer processing time |
| Improved uniformity and yield | Reduced defect density and rework costs |
| Reduced lithography complexity | Lower mask costs and fewer patterning steps |
Industry Adoption Timeline
- 2024–2025: Insertion for critical layers at 3nm nodes
- 2025–2026: Full adoption for gate and contact formation at 2nm nodes
- 2027+: Dominant etching technology for sub-2nm nodes