Atomfair 2 inch diameter Silicon Carbide (SiC) Substrate

A 2-inch SiC substrate available in industrial, research, and dummy grades. Designed for applications requiring high-power, high-temperature, or high-frequency performance. Features precise orientation and low micropipe density.

Description

A 2-inch SiC substrate available in industrial, research, and dummy grades. Designed for applications requiring high-power, high-temperature, or high-frequency performance. Features precise orientation and low micropipe density.

Parameter Industrial Grade (P Grade) Research Grade (R Grade) Dummy Grade (D Grade)
Diameter 50.8mmยฑ0.38mm 50.8mmยฑ0.38mm 50.8mmยฑ0.38mm
Thickness 350umยฑ25 um 350umยฑ25 um 350umยฑ25 um
Wafer Orientation Off axis: 2.0ยฐ-4.0ยฐ toward [1120] ยฑ0.5ยฐ (4H/6H-P), On axis:(111)ยฑ0.5ยฐ (3C-N) Off axis: 2.0ยฐ-4.0ยฐ toward [1120] ยฑ0.5ยฐ (4H/6H-P), On axis:(111)ยฑ0.5ยฐ (3C-N) Off axis: 2.0ยฐ-4.0ยฐ toward [1120] ยฑ0.5ยฐ (4H/6H-P), On axis:(111)ยฑ0.5ยฐ (3C-N)
Micropipe Density 0cmยฒ 0cmยฒ 0cmยฒ
Resistivity (4H/6H-P) โ‰ค0.10ฮฉยทcm โ‰ค0.10ฮฉยทcm โ‰ค0.10ฮฉยทcm
Resistivity (3C-N) โ‰ค0.8mฮฉยทcm โ‰ค0.8mฮฉยทcm โ‰ค0.8mฮฉยทcm
Primary Flat Orientation (4H/6H-P) {10-10}ยฑ5.0ยฐ {10-10}ยฑ5.0ยฐ {10-10}ยฑ5.0ยฐ
Primary Flat Orientation (3C-N) {1-10}ยฑ5.0ยฐ {1-10}ยฑ5.0ยฐ {1-10}ยฑ5.0ยฐ
Primary Flat Length 15.9mmยฑ1.7mm 15.9mmยฑ1.7mm 15.9mmยฑ1.7mm
Secondary Flat Length 8.0mmยฑ1.7mm 8.0mmยฑ1.7mm 8.0mmยฑ1.7mm
Secondary Flat Orientation 90ยฐ CW from Prime flat ยฑ5.0ยฐ 90ยฐ CW from Prime flat ยฑ5.0ยฐ 90ยฐ CW from Prime flat ยฑ5.0ยฐ
Edge Exclusion 3mm 3mm 3mm
TTV/Bow/Warp โ‰ค2.5ฮผm/โ‰ค5ฮผm/โ‰ค15ฮผm/โ‰ค30ฮผm โ‰ค2.5ฮผm/โ‰ค5ฮผm/โ‰ค15ฮผm/โ‰ค30ฮผm โ‰ค2.5ฮผm/โ‰ค5ฮผm/โ‰ค15ฮผm/โ‰ค30ฮผm
Surface Roughness (Polish) Raโ‰ค1 nm Raโ‰ค1 nm Raโ‰ค1 nm
Surface Roughness (CMP) Raโ‰ค0.2 nm Raโ‰ค0.2 nm Raโ‰ค0.2 nm
Edge Cracks None 1 allowed, โ‰ค1 mm None
Hex Plates โ‰ค1% cumulative area โ‰ค3% cumulative area โ‰ค3% cumulative area
Polytype Areas None โ‰ค2% cumulative area โ‰ค5% cumulative area
Si Surface Scratches โ‰ค3 scratches, โ‰ค1ร—wafer diameter cumulative length โ‰ค5 scratches, โ‰ค1ร—wafer diameter cumulative length โ‰ค8 scratches, โ‰ค1ร—wafer diameter cumulative length
Edge Chips None โ‰ค3 allowed, โ‰ค0.5 mm each โ‰ค5 allowed, โ‰ค1 mm each
Si Surface Contamination None None None
Packaging Multi-wafer Cassette or Single Wafer Container Multi-wafer Cassette or Single Wafer Container Multi-wafer Cassette or Single Wafer Container

If you are interested or have any questions, please contact us at inquiry@atomfair.com

Disclaimer: Sold exclusively for laboratory research.