Quantum computing and next-generation electronics

Through 3D monolithic integration to achieve high-density memory and logic stacking

3D integration semiconductor stacking memory technology logic circuits miniaturization

Revolutionizing semiconductor manufacturing through EUV mask defect mitigation and 3D monolithic integration

EUV lithography mask defects 3D integration semiconductor manufacturing chip scaling

Implementing hybrid bonding for chiplet integration in next-gen processors

hybrid bonding chiplet integration semiconductor packaging 3D ICs high-performance computing

Enhancing spintronic devices with topological insulators for ultra-low-power computing

topological insulators spintronics low-power computing

Using carbon nanotube vias to overcome interconnect bottlenecks in next-generation 3D chip stacking

carbon nanotubes 3D integration interconnects semiconductor scaling thermal dissipation

Leveraging ferroelectric hafnium oxide for ultra-low-power non-volatile memory devices

ferroelectric memory hafnium oxide non-volatile storage low-power electronics semiconductor materials

Hybrid bonding techniques for chiplet integration in next-generation GPUs

hybrid bonding chiplet integration GPU design 3D packaging interconnects

Using topological insulators for ultra-low-power spintronic memory devices

topological insulators spintronics memory devices energy efficiency quantum materials

Ferroelectric hafnium oxide for ultra-low-power computing in attojoule energy regimes

ferroelectric materials hafnium oxide low-power computing attojoule electronics semiconductor technology

Employing topological insulators for low-power spintronic memory devices

topological insulators spintronics quantum materials memory devices energy efficiency

Optimizing backside power delivery networks for 3D integrated circuits

power delivery 3D integration parasitic capacitance thermal management IC design

Through back-end-of-line thermal management for next-gen 3D chip stacking

3D IC cooling thermal management chip stacking semiconductor packaging heat dissipation