Fatigue behavior in semiconductors is a critical consideration for microelectromechanical systems (MEMS) and other applications where cyclic loading occurs. Unlike bulk materials, semiconductor devices often operate under high-frequency mechanical stress, making fatigue resistance a key reliability metric. The mechanisms of fatigue in single-crystal and polycrystalline semiconductors differ due to variations in grain boundaries, dislocation dynamics, and crack propagation pathways. Understanding these differences is essential for designing durable MEMS devices.

Crack initiation in semiconductors under cyclic loading typically begins at stress concentrators such as surface defects, notches, or grain boundaries. In single-crystal materials like silicon, dislocations play a dominant role. Under repeated stress, dislocations nucleate and multiply, forming slip bands that act as precursors to microcracks. The absence of grain boundaries means crack paths are more predictable, often following crystallographic planes. In contrast, polycrystalline semiconductors, such as polysilicon, exhibit more complex behavior. Grain boundaries act as barriers to dislocation motion, leading to stress concentrations that facilitate crack nucleation. The statistical nature of grain orientation and boundary distribution results in less predictable crack initiation sites.

Once a crack initiates, its propagation follows fracture mechanics principles, but the adaptation of Paris’ law for semiconductors requires careful consideration. Paris’ law, which describes crack growth rate as a function of stress intensity factor range, is traditionally applied to metals. For semiconductors, modifications account for brittle fracture tendencies and environmental effects. In single-crystal silicon, crack growth rates exhibit a strong dependence on stress intensity factor range, with a Paris exponent typically higher than in ductile materials. This reflects the low energy required for crack propagation in covalent crystals. Humidity further accelerates crack growth due to stress corrosion cracking mechanisms, where water molecules weaken Si-O bonds at the crack tip.

Polycrystalline materials introduce additional complexity. Crack propagation often follows intergranular paths, especially in materials with weak grain boundaries. The Paris exponent may vary significantly depending on grain size and boundary cohesion. Fine-grained materials can exhibit higher resistance to crack growth due to frequent crack deflection at boundaries, while coarse-grained structures may allow more direct propagation. Experimental studies on polysilicon MEMS devices have shown that fatigue life can be improved through grain boundary engineering, such as doping or annealing to enhance boundary strength.

Stress-life (S-N) curves provide a practical framework for predicting fatigue failure in semiconductor devices. These curves plot applied stress amplitude against the number of cycles to failure, revealing endurance limits and fatigue strengths. Single-crystal silicon displays a distinct endurance limit, below which fatigue failure does not occur regardless of cycle count. This limit is influenced by surface quality and environmental conditions. For instance, silicon in vacuum exhibits higher endurance limits than in humid air due to suppressed stress corrosion.

Polycrystalline semiconductors generally show more scatter in S-N data due to microstructural variability. The absence of a clear endurance limit is common, necessitating probabilistic design approaches. MEMS designers often use Weibull statistics to account for this variability, ensuring reliability across large populations of devices. Stress-life testing of polysilicon films has demonstrated that fatigue life can be extended by optimizing deposition conditions to control residual stress and grain morphology.

Comparative studies between single-crystal and polycrystalline systems highlight trade-offs in fatigue performance. Single-crystal silicon offers superior predictability and higher intrinsic fatigue resistance but is limited by fabrication costs and design flexibility. Polycrystalline materials, while more economical and versatile, require careful processing to mitigate fatigue vulnerabilities. Advances in deposition techniques, such as low-pressure chemical vapor deposition (LPCVD), have enabled finer grain control, narrowing the performance gap.

In MEMS applications, fatigue considerations influence device architecture and material selection. Resonators, accelerometers, and RF switches undergo millions of stress cycles, making fatigue a primary failure mode. Design strategies include minimizing stress concentrators through smooth geometries, using passivation layers to shield against environmental effects, and selecting materials with favorable grain structures. For polycrystalline devices, post-fabrication treatments like annealing can relieve residual stresses and improve fatigue life.

Emerging research explores nanoscale fatigue mechanisms, where surface effects dominate. Thin films and nanostructures exhibit size-dependent fatigue behavior, with smaller features often showing enhanced resistance due to constrained dislocation activity. This has implications for next-generation MEMS and NEMS devices, where dimensional scaling continues.

In summary, fatigue in semiconductors is governed by crack initiation at defects or grain boundaries, modified Paris’ law behavior reflecting brittle fracture, and stress-life relationships that differ between single-crystal and polycrystalline systems. MEMS design must account for these factors through material selection, processing optimization, and probabilistic reliability methods. Continued advancements in microstructure control and environmental protection will further enhance the fatigue resilience of semiconductor devices.