Thermal stress in semiconductor heterostructures arises due to differences in the coefficient of thermal expansion (CTE) between the substrate and the epitaxial layer. This mismatch becomes significant during temperature changes, such as during growth, processing, or device operation. The resulting thermal strain can lead to defects, cracking, or delamination, impacting device performance and reliability. Understanding the mechanisms of thermal stress, strain relaxation, and critical thickness is essential for designing robust semiconductor heterostructures.

The coefficient of thermal expansion describes how a material's dimensions change with temperature. When two materials with different CTEs are bonded, heating or cooling induces strain due to their unequal expansion or contraction. For a thin film on a substrate, the biaxial thermal strain is given by:
ε_thermal = (α_film - α_substrate) × ΔT
where α_film and α_substrate are the CTEs of the film and substrate, respectively, and ΔT is the temperature change. If α_film > α_substrate, cooling from the growth temperature results in compressive strain in the film. Conversely, if α_film < α_substrate, the film experiences tensile strain.

A classic example is the Si/Ge system. Silicon has a CTE of approximately 2.6 × 10^-6 K^-1, while germanium has a higher CTE of about 5.8 × 10^-6 K^-1. When a Ge layer is grown on a Si substrate and cooled from the growth temperature, the Ge contracts more than the Si, leading to compressive strain in the Ge layer. This strain can be partially accommodated elastically, but beyond a certain thickness, plastic relaxation occurs through misfit dislocation formation.

Another example is GaN grown on sapphire (Al2O3). GaN has a CTE of 5.6 × 10^-6 K^-1 along the a-axis and 3.2 × 10^-6 K^-1 along the c-axis, while sapphire has an anisotropic CTE of 7.5 × 10^-6 K^-1 along the a-axis and 8.5 × 10^-6 K^-1 along the c-axis. Upon cooling from growth temperatures (typically above 1000°C), the GaN layer experiences tensile strain due to the higher CTE of sapphire. This strain can lead to cracking if the film thickness exceeds the critical value for relaxation.

Strain relaxation occurs when the accumulated strain energy exceeds the energy required to form defects, such as misfit dislocations. The critical thickness (h_c) is the maximum film thickness that can be grown before strain relaxation via defect formation becomes energetically favorable. For a heterostructure with a small lattice mismatch, the Matthews-Blakeslee model provides an estimate of the critical thickness:
h_c = (b / 8πf)(1 - ν)/(1 + ν) ln(h_c / b + 1)
where b is the magnitude of the Burgers vector, f is the misfit strain, and ν is Poisson's ratio. For larger mismatches, the People-Bean model is often used:
h_c = (1.26 b^2)/(16π|f|^2 a) ln(h_c √2 / b)
where a is the lattice constant.

In the Si/Ge system, the lattice mismatch is about 4.2%, leading to a critical thickness of only a few nanometers for fully strained Ge layers. Beyond this thickness, misfit dislocations form at the interface to relieve strain. For GaN/sapphire, despite the large CTE mismatch, the absence of a significant lattice mismatch means that thermal stress dominates. The critical thickness for crack formation in GaN on sapphire is typically in the range of micrometers, depending on growth conditions and cooling rates.

Thermal stress can also lead to wafer bowing, where the substrate bends to accommodate the strain in the epitaxial layer. The radius of curvature (R) due to thermal stress can be estimated using Stoney's equation:
R = (E_substrate t_substrate^2)/(6 σ_film t_film (1 - ν_substrate))
where E_substrate is the Young's modulus of the substrate, t_substrate and t_film are the thicknesses of the substrate and film, σ_film is the stress in the film, and ν_substrate is Poisson's ratio of the substrate. For GaN on sapphire, the high thermal stress often results in significant bowing, complicating subsequent processing steps.

To mitigate thermal stress, several strategies can be employed. Graded layers or superlattices can distribute the strain over multiple interfaces, reducing the risk of cracking. Compliant substrates, such as those with engineered porosity or buffer layers, can absorb some of the strain. For example, AlN or low-temperature GaN buffer layers are commonly used in GaN/sapphire systems to reduce dislocation density and manage thermal stress. In Si/Ge systems, strain-relaxed buffers (SRBs) or virtual substrates with intermediate compositions (e.g., SiGe graded layers) help accommodate the mismatch.

Thermal cycling, where the heterostructure undergoes repeated heating and cooling, can exacerbate stress-related degradation. Dislocations may propagate or multiply, and interfacial delamination can occur over time. In power electronics or high-temperature applications, such as GaN-based devices, thermal stress management is critical for long-term reliability. Finite element modeling (FEM) is often used to simulate thermal stress distributions and predict failure modes in complex heterostructures.

In summary, thermal stress in semiconductor heterostructures is a critical consideration for device design and fabrication. The CTE mismatch between materials determines the nature and magnitude of thermal strain, while the critical thickness defines the limits of elastic strain accommodation. Systems like Si/Ge and GaN/sapphire illustrate the challenges posed by thermal stress and the importance of strain engineering. By employing buffer layers, graded compositions, and compliant substrates, thermal stress can be managed to enhance device performance and durability.