Deep-level transient spectroscopy (DLTS) is a high-sensitivity technique for characterizing electrically active defects in semiconductors. Reproducible measurements require strict adherence to standardized protocols, covering sample preparation, bias conditions, and temperature control. The following outlines a generalized framework applicable to most semiconductor systems.
Sample Preparation
The sample must form a rectifying junction, typically a Schottky diode or p-n junction. For Schottky contacts, the semiconductor surface is first cleaned with a sequence of organic solvents (e.g., acetone, isopropanol) followed by a dilute acid etch to remove native oxides. For silicon, a 5% HF dip for 30 seconds is typical. Metal deposition is performed via electron-beam evaporation or sputtering under high vacuum (<1×10⁻⁶ Torr) to minimize interfacial contamination. Ohmic contacts on the backside are formed using low-resistance metals (e.g., AuGe/Ni for n-type GaAs, Ti/Al for n-type Si) annealed at temperatures between 300°C and 450°C for 1–5 minutes. Junction area should be 0.01–1 mm² to limit capacitance while ensuring measurable signal intensity.
Bias Conditions
The junction is reverse-biased to establish a depletion region. The quiescent bias (V₀) is selected such that the depletion width exceeds the expected defect depth but avoids breakdown. A typical starting point is 50–90% of the breakdown voltage. The filling pulse (Vₚ) temporarily forward-biases the junction or reduces reverse bias to inject minority carriers. Pulse height is adjusted to ensure defect states are fully populated; common values range from 0 V to slight forward bias (+0.3 V to +1 V). Pulse width (tₚ) must exceed the emission time constant of the deepest trap of interest, usually 1 ms to 10 ms. Shorter pulses may miss slow-emission defects, while excessively long pulses introduce heating artifacts.
Temperature Sweep
DLTS scans are performed over a temperature range where defect emission rates fall within the instrument’s detection window (typically 20 K–400 K). A linear sweep rate of 0.1–0.5 K/s balances resolution and measurement time. Rapid sweeps (>1 K/s) risk thermal lag, while slower rates (<0.05 K/s) prolong experiments unnecessarily. The sample stage must stabilize temperature to within ±0.1 K during each measurement point. Liquid nitrogen cryostats are standard for low-T measurements; resistive heaters extend the range to 500 K if needed.
Transient Acquisition
Capacitance transients are recorded after each filling pulse using a high-precision meter (resolution <0.1 fF). The sampling rate must capture the fastest expected transient; 1–10 MHz is typical. Baseline drift is minimized by averaging 10–100 transients per temperature point. The time window (t₁, t₂) for rate-window analysis is selected based on the defect’s expected emission rate (e.g., t₁=1 ms, t₂=10 ms for mid-gap traps in Si). Multiple rate windows (e.g., 2, 20, 200 ms⁻¹) help distinguish overlapping peaks.
Data Analysis
The DLTS signal (ΔC/C) is calculated as the difference in normalized capacitance at t₁ and t₂. Defect parameters are extracted via Arrhenius analysis of the emission rate (eₙₚ) versus inverse temperature:
eₙₚ = γₙₚσₙₚT²exp(–ΔEₜ/kT)
where γₙₚ is the material-specific prefactor, σₙₚ is the capture cross-section, ΔEₜ is the activation energy, and k is Boltzmann’s constant. A minimum of three rate-window scans are required to confirm the defect’s thermal signature. Concentration (Nₜ) is calculated from the peak amplitude:
Nₜ ≈ 2ΔC/C × N_D
where N_D is the doping density. Systematic errors arise if Nₜ exceeds 10% of N_D due to depletion width modulation.
Error Mitigation
Key sources of error and mitigation strategies include:
- Series resistance: Keep below 100 Ω by optimizing ohmic contacts. Correct using equivalent circuit models if unavoidable.
- Non-ideal transients: Exponential fits with χ²<1.1 indicate single-trap dominance. Multi-exponential decays suggest defect clusters.
- Electric field effects: For high fields (>10⁴ V/cm), Poole-Frenkel corrections must be applied to ΔEₜ.
- Surface contamination: Leakage currents >1 nA invalidate capacitance data; re-clean contacts if observed.
Calibration
System calibration is verified using a reference sample with known defects (e.g., Au-doped Si with Eₜ=0.54 eV). The measured ΔEₜ should match within ±0.02 eV. Temperature sensors are calibrated against a NIST-traceable standard quarterly.
Reporting Standards
Publications should include:
1. Junction type and contact fabrication details
2. Bias conditions (V₀, Vₚ, tₚ)
3. Sweep rate and temperature range
4. Rate window settings
5. Raw and Arrhenius plots with fit parameters
6. Estimated uncertainty in ΔEₜ (±0.01–0.05 eV typical)
This protocol ensures cross-lab reproducibility when adapted to specific materials. Variations in pulse shaping or lock-in-based DLTS require additional documentation of modulation parameters but follow the same core principles.