Deep-level transient spectroscopy (DLTS) is a critical tool for investigating electrically active defects in semiconductors, particularly under electrical bias stress conditions. In metal-oxide-semiconductor field-effect transistors (MOSFETs) and high-electron-mobility transistors (HEMTs), defect generation and transformation under electrical stress directly impact device reliability. Understanding the activation mechanisms of these traps is essential for improving device performance and longevity.

Electrical bias stress induces defects in semiconductor materials through several mechanisms, including hot carrier injection, bias temperature instability, and trap-assisted tunneling. DLTS provides a high-sensitivity method to characterize these defects by measuring their emission kinetics as a function of temperature. The technique identifies defect energy levels, capture cross-sections, and concentrations, offering insights into their microscopic origins.

In MOSFETs, gate oxide degradation under bias stress is a major concern. Silicon dangling bonds (Pb centers) and oxygen vacancies are common defects that form at the Si-SiO2 interface. DLTS studies reveal that positive bias temperature instability (PBTI) in n-MOSFETs generates oxide traps with energy levels near the conduction band edge. These traps exhibit distinct DLTS signatures, with activation energies ranging from 0.3 to 0.6 eV. Negative bias temperature instability (NBTI) in p-MOSFETs, on the other hand, involves interface state generation with activation energies between 0.1 and 0.4 eV. The transformation of precursor defects into active traps under prolonged stress is detectable through DLTS transients, showing an increase in trap density over time.

HEMTs, particularly those based on GaN, face defect-related challenges due to high electric fields and piezoelectric effects. DLTS investigations of AlGaN/GaN HEMTs identify traps associated with nitrogen vacancies, carbon impurities, and dislocation-related states. Under high-voltage stress, these defects can undergo structural changes, leading to increased leakage currents and threshold voltage shifts. DLTS spectra of stressed GaN HEMTs reveal deep-level traps with activation energies between 0.2 and 1.0 eV, some of which are linked to surface states or buffer layer defects.

Trap activation mechanisms vary depending on material composition and stress conditions. In silicon devices, hydrogen plays a significant role in defect passivation and depassivation. Electrical stress can break Si-H bonds, releasing hydrogen and reactivating pre-existing traps. DLTS measurements confirm this by showing an increase in interface state density after stress, correlating with hydrogen desorption. In GaN devices, electron trapping is often associated with threading dislocations, which act as preferential sites for defect formation. DLTS data indicates that these traps have large capture cross-sections, making them particularly detrimental under high-field operation.

The kinetics of defect generation can be further analyzed using DLTS by varying the filling pulse duration and bias conditions. This approach distinguishes between fast and slow traps, providing information on their spatial distribution within the device. For example, in MOSFETs, bulk oxide traps exhibit slower emission rates compared to interface states, allowing DLTS to separate their contributions. In HEMTs, traps near the two-dimensional electron gas (2DEG) region show strong bias dependence, with their DLTS peaks shifting as a function of applied voltage.

Temperature-dependent DLTS studies are crucial for understanding the thermal stability of defects. Some traps are only observable at elevated temperatures, indicating a high energy barrier for emission. In SiC power devices, for instance, DLTS reveals deep levels related to intrinsic defects such as silicon vacancies, which become more pronounced under electrical stress. The activation energies of these traps range from 0.4 to 1.6 eV, with some exhibiting metastable behavior under cyclic stress.

The transformation of defects under electrical stress is not always permanent. Some traps can be annealed out at higher temperatures or under reverse bias, as observed in DLTS recovery experiments. This reversible behavior is particularly relevant for device reliability, as it suggests that certain degradation mechanisms may be mitigated through optimized operation conditions. However, other defects remain stable once formed, leading to irreversible performance degradation.

DLTS also plays a key role in identifying the microscopic structure of defects. By combining DLTS with other characterization techniques such as electron paramagnetic resonance (EPR), specific defect configurations can be correlated with their electrical signatures. For example, the E1 and E2 centers in irradiated silicon have been linked to vacancy-oxygen complexes, with DLTS confirming their energy levels at Ec - 0.18 eV and Ec - 0.42 eV, respectively.

In conclusion, DLTS provides invaluable insights into defect generation and transformation under electrical bias stress in MOSFETs and HEMTs. By analyzing trap activation mechanisms, capture kinetics, and thermal stability, this technique helps identify the root causes of device degradation. Continued advancements in DLTS methodology will further enhance its ability to probe defects at smaller scales and under more complex stress conditions, contributing to the development of more reliable semiconductor devices.